This invention relates generally to a communication control circuit in a system using a Centronics compatible parallel interface. In particular, this invention relates to a circuit for generating an acknowledge signal and a busy signal, wherein the above two signals control sending and receiving of the communication data between at least two communication stations.
Generally, a laser printer, for example, using a Centronics compatible parallel interface has a specific data communication method of communicating data between communication systems, which follows basically the regulation of the Centronics. For instance, in a conventional method, when data is transmitted from another data communication device, strobe signal S.sub.1 output from a Centronics interface cable 30 will be transmitted together with the data communication signal, as illustrated in FIG. 1. If the strobe signal S.sub.1 is generated, a busy signal S.sub.2 of the logic high state will be generated to prevent transmission of different data until the data processing of the data transmitted currently is completely executed by a CPU 10. In this case, the busy signal S.sub.2 is applied to an interrupt terminal of the CPU 10 so as to inform the CPU 10 of incoming data. Then, the CPU 10 starts to read in the data received from the other data communication device and generates an acknowledge signal S.sub.3 from an output port Y.sub.1 thereof to an acknowledge terminal ACK of the Centronics interface cable 30 in order to send it to the other data communication device so that the completion of the data receiving may be indicated to the other data communication device.
At about the same moment, the busy signal S.sub.2 of the logic high, generated by the busy signal generator 20, will make a transition from the logic high to low in order to prepare for other data receiving. On the other hand, if the CPU 10 is unable to receive the data, the busy signal S.sub.2 must be switched to the logic high again.
For instance, if the busy signal generator 20 produces the busy signal S.sub.2 under the control of a first control signal S.sub.5 which controls the generation and release of the busy condition according to the CPU 10, then the busy signal S.sub.2 and a second control signal S.sub.6 generated from the CPU 10 are provided to an OR gate G.sub.1 which applies the logical result thereof to a busy terminal BUSY of the Centronics interface cable 30. In the meantime, the second control signal S.sub.6 is used for generating or releasing the busy condition according to the CPU 10.
With respect to the timing relation of the acknowledge signal S.sub.3 and busy signal S.sub.2 data receiving, when considered in the place of the other data communication device (a transmitter), the busy signal S.sub.2 of the receiver (in this case, the system of FIG. 1) becomes the logic low state after the transmitter sends out one frame of data. If the transmitter receives the acknowledge signal S.sub.3 generated from the receiver, the transmitter will be ready to send another frame of data. It should be noted that these operations are controlled by the CPU 10 by means of software.
As illustrated in FIG. 3, the system shown in FIG. 1 receives data at time point t.sub.1, reads in the data with the CPU 10 at time point t.sub.2 and releases the busy signal S.sub.2 and generates the acknowledge signal S.sub.3 in sequence at time point t.sub.3 through the output port, so that the system informs the receiver that the system is ready to receive more data.
If the transmitter transmits the next data at the instance of time point t.sub.3 , then again the CPU 10 of the receiver is provided with the busy signal S.sub.2 generated by the busy signal generator 20. According to the conventional method as shown in FIG. 3, however, if the next data is transmitted from the transmitter at the time point t.sub.3 at which the busy signal S.sub.2 and the acknowledge signal S.sub.3 change to logic low, a predetermined time is required for the acknowledge signal S.sub.3 to change to logic high, which may cause mis-operation of the CPU 10 because the data processing should not be made while the acknowledge signal S.sub.3 is still at the logic low state.
To alleviate this problem, there is proposed a method of delaying the busy signal S.sub.2 until the acknowledge signal S.sub.3 changes to the logic high at time point t.sub.4. In this case, however, there arises another problem that, in some cases, the so-called hand-shaking is executed by only the strobe signal S.sub.1 and acknowledge signal S.sub.3. Furthermore, when the acknowledge signal S.sub.3 is processed in the CPU 10 by the software, the acknowledge signal S.sub.3 stays at the logic low state for about 10 .mu.sec during which the CPU 10 generates only the acknowledge signal S.sub.3 without processing other data. Therefore, the system performance is deteriorated overall.
Moreover, in the event that the busy signal S.sub.2 and acknowledge signal S.sub.3 are all dealt with by the software processing as illustrated in FIGS. 3 and 4, the output will be produced from output port Y.sub.0 and output port Y.sub.1 of the CPU 10, that may cause a relatively long execution time. Such a delay may be considered a negligible amount in some cases, however when it comes to a situation which should handle a great deal of data to be transmitted therethrough, the system performance will be influenced significantly.